Transistors of Semiconductor Devices and Methods of Fabricating the Same

ABSTRACT

Transistors and methods of fabricating transistors are disclosed. A disclosed method comprises forming an inversion epitaxial layer on a silicon substrate; forming a hard mask on the inversion epitaxial layer; depositing a silicon epitaxial layer over the inversion epitaxial layer; forming a trench through the silicon epitaxial layer by removing the hard mask; forming reverse spacers on the sidewalls of the trench by filling the trench with an insulating layer and etching the insulating layer; forming a gate electrode over the reverse spacers; forming pocket-well regions and LDD regions in the silicon substrate by performing ion implantations; forming spacers on the sidewalls of the gate electrode; forming source and drain regions in the silicon substrate by performing an ion implantation; and forming a silicide layer on the gate electrode and the source and drain regions.

CROSS REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. application Ser. No.11/027,518, filed Dec. 30, 2004, which is incorporated herein byreference in its entirety.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to semiconductor devices and,more particularly, to transistors of semiconductor devices and methodsof fabricating the same.

BACKGROUND

In a metal-oxide-semiconductor (MOS) transistor such as a MOSfield-effect-transistor (MOSFET), electric current flows through asurface region under a gate electrode and a gate oxide when an electricfield is applied to the source and drain junction regions while a gatecharge is applied. The surface region through which the electric currentflows is known as a channel. The characteristics of a MOSFET aredetermined by a dopant concentration in the channel. More specifically,it is very important to precisely dope impurities into the channelregion because device characteristics such as the threshold voltage ofthe transistor and the drain current are subject to the dopantconcentration.

Conventional channel doping is achieved by performing well ionimplantation, channel ion implantation, or threshold ion implantation.Channel structures formed by such ion implantation include a flatchannel in which a dopant concentration is uniform through the wholeregion of the channel, a buried channel which is formed at apredetermined distance from the top surface of a semiconductorsubstrate, and a retrograde channel which has a vertically increasingdoping profile from the top surface of the channel. Retrograde channelsare widely used for high performance microprocessors requiring a channellength less than 0.2 μm. In such a context, the retrograde channel isgenerally formed by heavy ion implantation using indium (In), arsenic(As), or antimony (Sb). The retrograde channel is suitable for highperformance MOSFET devices with high driving current characteristicsbecause a low dopant concentration in its surface increases the surfacemobility of an electric current.

As the degree of integration of a semiconductor device increase, thechannel length is shortened, and a very thin channel is required.However, conventional ion implantation technology cannot achieve aretrograde channel less than 50 nm in depth. To solve such a problem, anepitaxial channel has been suggested. However, the epitaxial channel hasnot achieved an improvement in the current on-off characteristicsbecause it is difficult to control the loss and diffusion of the channeldopants due to an epitaxial layer formation process and a later thermaltreatment process.

The most ideal channel doping method may embody a 6-doped epitaxialchannel. However, according to the reported findings, both doped andundoped epitaxial layers cannot be made into a 6-doped epitaxial channelless than 30 nm in depth because of later dopant diffusion.

To solve such a problem, a method for preventing diffusion of dopants ina δ-doped layer has been suggested in Lee and Lee, Laser ThermalAnnealed SSR Well Prior to Epi-Channel Growth (LASPE) for 70 nm nFET,IEDM 2000. The suggested method performs channel doping by using anultra-low energy ion implantation and an instant laser annealing.According to the suggested method, the instant laser annealing controlsthe diffusion and loss of dopants during a selective epitaxial growth.

However, the laser power for the laser annealing may cause partialmelting of the silicon substrate surface, thereby deteriorating thesurface roughness and causing crystal defects. Therefore, the laserannealing method is not applicable to practical semiconductor devicemanufacturing processes.

FIG. 1 is a cross-sectional view of a conventional transistor having asuper steep retrograde (SSR) epitaxial channel. Although conventionaltransistor fabrication technology has reduced the depth of the channelby forming a retrograde channel 7 as shown in FIG. 1, it has failed tosubstantially reduce the length of the channel.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a conventional transistor having anSSR epitaxial channel.

FIGS. 2 a through 2 e are cross-sectional views illustrating an exampleprocess of fabricating a transistor of a semiconductor device having anSSR epitaxial channel and reverse spacers performed in accordance withthe teachings of the present invention.

DETAILED DESCRIPTION

FIGS. 2 a through 2 e are cross-sectional views illustrating an exampleprocess of fabricating a transistor of a semiconductor device having anSSR epitaxial channel and reverse spacers. Referring to FIG. 2 a, aninversion epitaxial layer 11 is formed over a silicon substrate 10. Theinversion epitaxial layer 11 is used as an SSR epitaxial channel.

Referring to FIG. 2 b, a hard mask 12 is formed on the inversionepitaxial layer 11. The hard mask 12 covers an area for reverse spacersto be formed by a later unit process.

Referring to FIG. 2 c, a silicon epitaxial layer 14 is formed over theinversion epitaxial layer 11, but not on the area covered by the hardmask. The hard mask is then removed to form a trench through the siliconepitaxial layer 14. The trench is filled with an insulating layer. Theinsulating layer is then dry-etched to form reverse spacers 13 on thesidewalls of the trench. In the illustrated example process, the widthof the trench is smaller than the width of a gate electrode to be formedby a later unit process. The insulating layer is preferably a singlelayer of tetra ethyl ortho silicate (TEOS) or a multi-layer ofTEOS-SiN-TEOS.

Referring to FIG. 2 d, an oxide layer and a polysilicon layer aresequentially deposited over the structure of FIG. 2 c. Some portion(s)of the oxide layer and the polysilicon layer are removed by using a dryetching process to complete a gate oxide 15 and a gate electrode 16. Thegate electrode 16 is positioned above the inversion epitaxial layerbetween the reverse spacers. In the illustrated example process, thewidth of the gate electrode 16 is smaller than the width of the trench,but larger than the space between the reverse spacers 13. The length ofa channel under the gate electrode 16 is defined as the length of theSSR epitaxial channel 11 between the reverse spacers 13. By forming thereverse spacers 13 on the area for the gate electrode 16, theillustrated example process can considerably reduce the length of thechannel compared to a conventional process which forms a channel havingthe same length as the gate electrode. Therefore, the illustratedexample process is applicable to a fabrication process for a less than90 nm transistor.

Next, pocket-well regions (not shown) and lightly doped drain (LDD)regions 17 are formed in the silicon substrate 10 by performing a firstion implantation process. Generally, conventional technology mustimplant low energy ions in order to form a shallow junction to prevent aleakage current of the junction area. However, the illustrated exampleprocess can form a shallow junction even when high energy ions areimplanted because the silicon epitaxial layer 14 and the reverse spacers13 on the inversion epitaxial layer 11 function as a buffer layer duringthe first ion implantation.

Referring to FIG. 2 e, an insulating layer is deposited over thestructure of FIG. 2 d. An etching process is performed to form gatespacers 18 on the sidewalls of the gate electrode 16. A second ionimplantation process is then performed using the gate electrode 16 andthe gate spacers 18 as a mask to form deep source and drain regions 19in the silicon substrate 10. Particularly, the illustrated exampleprocess may form elevated source and drain regions because the secondion implantation process may implant ions into the silicon epitaxiallayer 14 on the source and drain regions 19. Moreover, because thesilicon epitaxial layer 14 functions as a buffer layer during the secondion implantation process, the described example process achieves theshallow junction necessary for a nanometer scale transistor design,thereby obviating the problem of parasitic capacitance due to theformation of the shallow junction. Subsequently, a silicide layer 20 isrespectively formed on the gate electrode 16 and on the source drainregions 19 by using a known unit process.

Consequently, a MOS transistor comprising an inversion epitaxial layeras an SSR epitaxial channel and elevated source and drain regions iscompleted. In detail, as shown in FIG. 2 e, after an inversion epitaxiallayer is formed on a semiconductor substrate, a trench is placed overthe inversion epitaxial layer and reverse spacers are positioned on thesidewalls of the trench. After a gate electrode is positioned above theinversion epitaxial layer between the reverse spacers, gate spacers areplaced on the sidewalls of the gate electrode. Pocket-well regions areformed under opposite sides of the gate electrode in the siliconsubstrate, and LDD regions are positioned adjacent the upper part of thepocket-well regions and the inversion epitaxial layer over thepocket-well regions. Source and drain regions, (which have a largerthickness than the LDD regions), are positioned adjacent the LDD regionsin the silicon substrate. A silicide layer is positioned on the gateelectrode and through the silicon epitaxial layer on the source anddrain regions, respectively.

From the foregoing, persons of ordinary skill in the art will appreciatethat the disclosed methods of fabricating a transistor of asemiconductor device simplify the manufacturing process and reduceproduction costs because they use an existing gate fabrication process.In other words, by depositing a silicon epitaxial layer before sourceand drain regions are formed in a silicon substrate and performing ionimplantation processes, the disclosed methods simplify the manufacturingprocess in comparison with a conventional selective epitaxial growthprocess requiring an additional ion implantation process.

From the foregoing, persons of ordinary skill in the art will furtherappreciate that, by forming an SSR epitaxial channel, a siliconepitaxial layer, and reverse spacers, the disclosed methods offabricating a transistor of a semiconductor device reduce parasiticcapacitance and a junction leakage current of a nanometer scale MOStransistors.

It is noted that this patent claims priority from Korean PatentApplication Serial Number 10-2003-0102038, which was filed on Dec. 31,2003, and is hereby incorporated by reference in its entirety.

Although certain example methods, apparatus and articles of manufacturehave been described herein, the scope of coverage of this patent is notlimited thereto. On the contrary, this patent covers all methods,apparatus and articles of manufacture fairly falling within the scope ofthe appended claims either literally or under the doctrine ofequivalents.

1. A method of fabricating a transistor, comprising: forming an inversion epitaxial layer on a silicon substrate; forming a hard mask on the inversion epitaxial layer; forming a silicon epitaxial layer over the inversion epitaxial layer; and forming a trench through the silicon epitaxial layer by removing the hard mask.
 2. The method as defined by claim 1, further comprising: filling the trench with an insulating layer; and forming reverse spacers on sidewalls of the trench by etching the insulating layer.
 3. The method as defined by claim 2, wherein the reverse spacers are formed by a dry etching process.
 4. The method as defined by claim 2, wherein the reverse spacers are formed of a single layer of TEOS or a multi-layer of TEOS-SiN-TEOS.
 5. The method as defined by claim 2, further comprising: forming a gate electrode over the reverse spacers, the gate electrode being positioned above the inversion epitaxial layer between the reverse spacers; and performing ion implantation using the gate electrode as a mask to form pocket-well regions and LDD regions.
 6. The method as defined by claim 5, further comprising: forming spacers on sidewalls of the gate electrode; forming source/drain regions by performing ion implantation using the gate electrode and the spacers as a mask; and forming a silicide layer on the gate electrode and the source and drain regions.
 7. The method as defined by claim 6, wherein the source and drain regions are elevated source and drain regions.
 8. The method as defined by claim 6, wherein the silicide layer on the source and drain regions is formed through the silicon epitaxial layer on the source and drain regions.
 9. The method as defined by claim 6, wherein the inversion epitaxial layer is used as an SSR epitaxial channel.
 10. The method as defined by claim 6, wherein a gate channel is located under the gate electrode, the gate channel having a length defined by a length of the inversion epitaxial layer exposed between the reverse spacers.
 11. The method as defined by claim 6, wherein the gate electrode has a width smaller than the trench and larger than a space between the reverse spacers. 